Specifications of semiconductor integrated circuit devices (hereinafter referred to as “semiconductor devices”) including microprocessor for computers have been made faster in operation speed and more multifunctional in recent years. Depending on such an increase in the operating speed and functions of semiconductor devices, the terminal pitch of a semiconductor device tends to be narrower and narrower. Accordingly, a finer wiring pattern is required for a packaging board or the like which is a printed wiring board for mounting a semiconductor device (hereinafter referred to as “packaging board or the like”) due to a decrease in the terminal pitch of the semiconductor devices.
In the packaging board or the like, interlayer connection between an outer-layer circuit (surface-layer circuit) where a semiconductor device is mounted and an inner-layer circuit is achieved by filled via-holes (non-perforated holes) and/or plated through-holes (perforated holes). For example, Patent Document 1 discloses a method for manufacturing the packaging board or the like in which interlayer connection between an outer layer and an inner layer is achieved by non-perforated holes and perforated-holes; a copper foil to be an outer layer is laminated on an inner-layer board on which the inner-layer circuit is formed via insulating layer, the non-perforated holes and the perforated-holes for interlayer connection are provided, and an electroless-plated copper layer and an electro-plated copper layer are formed inside of the non-perforated holes and the perforated-holes and on the outer-layer copper foil. In the method, inside of the non-perforated holes are filled-up by electroless-plated copper and electro-plated copper to finish filled via-holes. Next, a plated copper layer composed of an electroless-plated copper and an electro-plated copper having a specific thickness is formed on the inner walls of each through-hole. Then, an outer-layer circuit is formed by a subtractive method. By the way, a packaging board or the like in the current marketplace requires a fine wiring pattern with the pitch of 40 μm or less and line/space (hereinafter referred to as L/S) of 20 μm/20 μm or less for the outer-layer circuit, for example, as a measure to a decreasing terminal pitch of a semiconductor device.